Core Coupled Memory executable on STM32F4xx?
Trying to run code from a STM32F429s CCM but I always get a Hard Fault with the IBUSERR flag set as soon as I hit the first instruction in the CCM.
The instruction is valid and well aligned.
Is it possible that the STM32F4xx does not allow execution from the CCM? (Data access works well).
alios
embedded stm32
edited Nov 11 at 22:15
jubobs
32.7k17100124
asked Apr 11 at 6:39
alios
163
add a comment |
Trying to run code from a STM32F429s CCM but I always get a Hard Fault with the IBUSERR flag set as soon as I hit the first instruction in the CCM.
The instruction is valid and well aligned.
Is it possible that the STM32F4xx does not allow execution from the CCM? (Data access works well).
alios
embedded stm32
edited Nov 11 at 22:15
jubobs
32.7k17100124
asked Apr 11 at 6:39
alios
163
On this part the CCM has a performance advantage only when used to access data concurrently with DMA access to other on-chip memory by avoiding bus contention.
– Clifford
Apr 11 at 17:24
add a comment |
Trying to run code from a STM32F429s CCM but I always get a Hard Fault with the IBUSERR flag set as soon as I hit the first instruction in the CCM.
The instruction is valid and well aligned.
Is it possible that the STM32F4xx does not allow execution from the CCM? (Data access works well).
alios
embedded stm32
edited Nov 11 at 22:15
jubobs
32.7k17100124
asked Apr 11 at 6:39
alios
163
Trying to run code from a STM32F429s CCM but I always get a Hard Fault with the IBUSERR flag set as soon as I hit the first instruction in the CCM.
The instruction is valid and well aligned.
Is it possible that the STM32F4xx does not allow execution from the CCM? (Data access works well).
alios
embedded stm32
embedded stm32
edited Nov 11 at 22:15
jubobs
32.7k17100124
asked Apr 11 at 6:39
alios
163
edited Nov 11 at 22:15
jubobs
32.7k17100124
asked Apr 11 at 6:39
alios
163
edited Nov 11 at 22:15
jubobs
32.7k17100124
edited Nov 11 at 22:15
jubobs
32.7k17100124
edited Nov 11 at 22:15
jubobs
32.7k17100124
32.7k17100124
asked Apr 11 at 6:39
alios
163
asked Apr 11 at 6:39
alios
163
asked Apr 11 at 6:39
alios
163
163
On this part the CCM has a performance advantage only when used to access data concurrently with DMA access to other on-chip memory by avoiding bus contention.
– Clifford
Apr 11 at 17:24
add a comment |
On this part the CCM has a performance advantage only when used to access data concurrently with DMA access to other on-chip memory by avoiding bus contention.
– Clifford
Apr 11 at 17:24
On this part the CCM has a performance advantage only when used to access data concurrently with DMA access to other on-chip memory by avoiding bus contention.
– Clifford
Apr 11 at 17:24
On this part the CCM has a performance advantage only when used to access data concurrently with DMA access to other on-chip memory by avoiding bus contention.
– Clifford
Apr 11 at 17:24
add a comment |
1 Answer
1
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The CCM in these parts is only connected to the data bus. Instructions cannot be fetched from this memory -- only flash memory, SRAM1, and external memory should be used for code.
For more information, refer to section 2.1 ("System Architecture") of the reference manual, which is where the above image came from.
answered Apr 11 at 6:45
duskwuff
145k19176229
Thnx! On the STM32F3 it was also possible to run code from there.
– alios
Apr 11 at 7:13
But you can run from the SRAM. Place the critical routines there and stack and data in thew CCM - this is most efficient way to handle the critical routines.
– P__J__
Apr 11 at 10:41
@Clifford Are you sure? The sections on the I-bus and S-bus explicitly mention fetching instructions; the section on the D-bus, by contrast, does not. It says that the target is "memory containing code or data", but that seems like it's in reference to the D-bus's use for literal data loads.
– duskwuff
Apr 11 at 15:37
@duskwuff : I stand corrected - the D-Bus allows data and debug access to code space, not execution. It is more clearly explained at infocenter.arm.com/help/index.jsp?topic=/…, though somewhat unhelpfully ST have used slightly different nomenclature.
– Clifford
Apr 11 at 17:09
1
@PeterJ_01 : I am not sure of your objection. That is what "I stand corrected" means - the change is clearly flagged. I deleted the original comments because a read might not get past that and be mislead.
– Clifford
Apr 11 at 19:27
|
show 9 more comments
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1 Answer
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active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
The CCM in these parts is only connected to the data bus. Instructions cannot be fetched from this memory -- only flash memory, SRAM1, and external memory should be used for code.
For more information, refer to section 2.1 ("System Architecture") of the reference manual, which is where the above image came from.
answered Apr 11 at 6:45
duskwuff
145k19176229
Thnx! On the STM32F3 it was also possible to run code from there.
– alios
Apr 11 at 7:13
But you can run from the SRAM. Place the critical routines there and stack and data in thew CCM - this is most efficient way to handle the critical routines.
– P__J__
Apr 11 at 10:41
@Clifford Are you sure? The sections on the I-bus and S-bus explicitly mention fetching instructions; the section on the D-bus, by contrast, does not. It says that the target is "memory containing code or data", but that seems like it's in reference to the D-bus's use for literal data loads.
– duskwuff
Apr 11 at 15:37
@duskwuff : I stand corrected - the D-Bus allows data and debug access to code space, not execution. It is more clearly explained at infocenter.arm.com/help/index.jsp?topic=/…, though somewhat unhelpfully ST have used slightly different nomenclature.
– Clifford
Apr 11 at 17:09
1
@PeterJ_01 : I am not sure of your objection. That is what "I stand corrected" means - the change is clearly flagged. I deleted the original comments because a read might not get past that and be mislead.
– Clifford
Apr 11 at 19:27
|
show 9 more comments
The CCM in these parts is only connected to the data bus. Instructions cannot be fetched from this memory -- only flash memory, SRAM1, and external memory should be used for code.
For more information, refer to section 2.1 ("System Architecture") of the reference manual, which is where the above image came from.
answered Apr 11 at 6:45
duskwuff
145k19176229
Thnx! On the STM32F3 it was also possible to run code from there.
– alios
Apr 11 at 7:13
But you can run from the SRAM. Place the critical routines there and stack and data in thew CCM - this is most efficient way to handle the critical routines.
– P__J__
Apr 11 at 10:41
@Clifford Are you sure? The sections on the I-bus and S-bus explicitly mention fetching instructions; the section on the D-bus, by contrast, does not. It says that the target is "memory containing code or data", but that seems like it's in reference to the D-bus's use for literal data loads.
– duskwuff
Apr 11 at 15:37
@duskwuff : I stand corrected - the D-Bus allows data and debug access to code space, not execution. It is more clearly explained at infocenter.arm.com/help/index.jsp?topic=/…, though somewhat unhelpfully ST have used slightly different nomenclature.
– Clifford
Apr 11 at 17:09
1
@PeterJ_01 : I am not sure of your objection. That is what "I stand corrected" means - the change is clearly flagged. I deleted the original comments because a read might not get past that and be mislead.
– Clifford
Apr 11 at 19:27
|
show 9 more comments
The CCM in these parts is only connected to the data bus. Instructions cannot be fetched from this memory -- only flash memory, SRAM1, and external memory should be used for code.
For more information, refer to section 2.1 ("System Architecture") of the reference manual, which is where the above image came from.
answered Apr 11 at 6:45
duskwuff
145k19176229
The CCM in these parts is only connected to the data bus. Instructions cannot be fetched from this memory -- only flash memory, SRAM1, and external memory should be used for code.
For more information, refer to section 2.1 ("System Architecture") of the reference manual, which is where the above image came from.
answered Apr 11 at 6:45
duskwuff
145k19176229
answered Apr 11 at 6:45
duskwuff
145k19176229
answered Apr 11 at 6:45
duskwuff
145k19176229
answered Apr 11 at 6:45
duskwuff
145k19176229
145k19176229
Thnx! On the STM32F3 it was also possible to run code from there.
– alios
Apr 11 at 7:13
But you can run from the SRAM. Place the critical routines there and stack and data in thew CCM - this is most efficient way to handle the critical routines.
– P__J__
Apr 11 at 10:41
@Clifford Are you sure? The sections on the I-bus and S-bus explicitly mention fetching instructions; the section on the D-bus, by contrast, does not. It says that the target is "memory containing code or data", but that seems like it's in reference to the D-bus's use for literal data loads.
– duskwuff
Apr 11 at 15:37
@duskwuff : I stand corrected - the D-Bus allows data and debug access to code space, not execution. It is more clearly explained at infocenter.arm.com/help/index.jsp?topic=/…, though somewhat unhelpfully ST have used slightly different nomenclature.
– Clifford
Apr 11 at 17:09
1
@PeterJ_01 : I am not sure of your objection. That is what "I stand corrected" means - the change is clearly flagged. I deleted the original comments because a read might not get past that and be mislead.
– Clifford
Apr 11 at 19:27
|
show 9 more comments
Thnx! On the STM32F3 it was also possible to run code from there.
– alios
Apr 11 at 7:13
But you can run from the SRAM. Place the critical routines there and stack and data in thew CCM - this is most efficient way to handle the critical routines.
– P__J__
Apr 11 at 10:41
@Clifford Are you sure? The sections on the I-bus and S-bus explicitly mention fetching instructions; the section on the D-bus, by contrast, does not. It says that the target is "memory containing code or data", but that seems like it's in reference to the D-bus's use for literal data loads.
– duskwuff
Apr 11 at 15:37
@duskwuff : I stand corrected - the D-Bus allows data and debug access to code space, not execution. It is more clearly explained at infocenter.arm.com/help/index.jsp?topic=/…, though somewhat unhelpfully ST have used slightly different nomenclature.
– Clifford
Apr 11 at 17:09
1
@PeterJ_01 : I am not sure of your objection. That is what "I stand corrected" means - the change is clearly flagged. I deleted the original comments because a read might not get past that and be mislead.
– Clifford
Apr 11 at 19:27
Thnx! On the STM32F3 it was also possible to run code from there.
– alios
Apr 11 at 7:13
Thnx! On the STM32F3 it was also possible to run code from there.
– alios
Apr 11 at 7:13
But you can run from the SRAM. Place the critical routines there and stack and data in thew CCM - this is most efficient way to handle the critical routines.
– P__J__
Apr 11 at 10:41
But you can run from the SRAM. Place the critical routines there and stack and data in thew CCM - this is most efficient way to handle the critical routines.
– P__J__
Apr 11 at 10:41
@Clifford Are you sure? The sections on the I-bus and S-bus explicitly mention fetching instructions; the section on the D-bus, by contrast, does not. It says that the target is "memory containing code or data", but that seems like it's in reference to the D-bus's use for literal data loads.
– duskwuff
Apr 11 at 15:37
@Clifford Are you sure? The sections on the I-bus and S-bus explicitly mention fetching instructions; the section on the D-bus, by contrast, does not. It says that the target is "memory containing code or data", but that seems like it's in reference to the D-bus's use for literal data loads.
– duskwuff
Apr 11 at 15:37
@duskwuff : I stand corrected - the D-Bus allows data and debug access to code space, not execution. It is more clearly explained at infocenter.arm.com/help/index.jsp?topic=/…, though somewhat unhelpfully ST have used slightly different nomenclature.
– Clifford
Apr 11 at 17:09
@duskwuff : I stand corrected - the D-Bus allows data and debug access to code space, not execution. It is more clearly explained at infocenter.arm.com/help/index.jsp?topic=/…, though somewhat unhelpfully ST have used slightly different nomenclature.
– Clifford
Apr 11 at 17:09
1
1
@PeterJ_01 : I am not sure of your objection. That is what "I stand corrected" means - the change is clearly flagged. I deleted the original comments because a read might not get past that and be mislead.
– Clifford
Apr 11 at 19:27
@PeterJ_01 : I am not sure of your objection. That is what "I stand corrected" means - the change is clearly flagged. I deleted the original comments because a read might not get past that and be mislead.
– Clifford
Apr 11 at 19:27
|
show 9 more comments
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On this part the CCM has a performance advantage only when used to access data concurrently with DMA access to other on-chip memory by avoiding bus contention.
– Clifford
Apr 11 at 17:24