Verilog d flipflop circuit testing
I'm trying to construct a structural implementation of a circuit that consists of a d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is exclusive or'd with the current state, and used as the input to the d flip flop. and it'll use the result state from the flipflop in the next run, etc. But I'm not too sure how to construct it.
The circuit looks like so:
module dff(D,clk,q);
input D,clk;
output q;
reg q;
always @ (posedge clk)
begin
q<=D;
end
endmodule
I'm pretty sure the d flip flop code is correct but when I try to test this my d and state values are just x for some reason. When I put in different x and y values in my testbench nothing happens, "state" and "d" just always says it has value "1'hx" in the simulation. Why is this happening and how do I actually assign an value to them?
testing verilog circuit flip-flop
asked Nov 11 at 21:53
dshawn
566
add a comment |
I'm trying to construct a structural implementation of a circuit that consists of a d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is exclusive or'd with the current state, and used as the input to the d flip flop. and it'll use the result state from the flipflop in the next run, etc. But I'm not too sure how to construct it.
The circuit looks like so:
module dff(D,clk,q);
input D,clk;
output q;
reg q;
always @ (posedge clk)
begin
q<=D;
end
endmodule
I'm pretty sure the d flip flop code is correct but when I try to test this my d and state values are just x for some reason. When I put in different x and y values in my testbench nothing happens, "state" and "d" just always says it has value "1'hx" in the simulation. Why is this happening and how do I actually assign an value to them?
testing verilog circuit flip-flop
asked Nov 11 at 21:53
dshawn
566
1
Are you sure you are running the clock signal? Please add you testbench code to your question so we can help you better
– Unn
Nov 11 at 23:11
crossposted electronics.stackexchange.com/questions/406245/…
– toolic
Nov 12 at 13:51
add a comment |
I'm trying to construct a structural implementation of a circuit that consists of a d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is exclusive or'd with the current state, and used as the input to the d flip flop. and it'll use the result state from the flipflop in the next run, etc. But I'm not too sure how to construct it.
The circuit looks like so:
module dff(D,clk,q);
input D,clk;
output q;
reg q;
always @ (posedge clk)
begin
q<=D;
end
endmodule
I'm pretty sure the d flip flop code is correct but when I try to test this my d and state values are just x for some reason. When I put in different x and y values in my testbench nothing happens, "state" and "d" just always says it has value "1'hx" in the simulation. Why is this happening and how do I actually assign an value to them?
testing verilog circuit flip-flop
asked Nov 11 at 21:53
dshawn
566
I'm trying to construct a structural implementation of a circuit that consists of a d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is exclusive or'd with the current state, and used as the input to the d flip flop. and it'll use the result state from the flipflop in the next run, etc. But I'm not too sure how to construct it.
The circuit looks like so:
module dff(D,clk,q);
input D,clk;
output q;
reg q;
always @ (posedge clk)
begin
q<=D;
end
endmodule
I'm pretty sure the d flip flop code is correct but when I try to test this my d and state values are just x for some reason. When I put in different x and y values in my testbench nothing happens, "state" and "d" just always says it has value "1'hx" in the simulation. Why is this happening and how do I actually assign an value to them?
testing verilog circuit flip-flop
testing verilog circuit flip-flop
asked Nov 11 at 21:53
dshawn
566
asked Nov 11 at 21:53
dshawn
566
edited Nov 12 at 17:18
asked Nov 11 at 21:53
dshawn
566
asked Nov 11 at 21:53
dshawn
566
asked Nov 11 at 21:53
dshawn
566
566
1
Are you sure you are running the clock signal? Please add you testbench code to your question so we can help you better
– Unn
Nov 11 at 23:11
crossposted electronics.stackexchange.com/questions/406245/…
– toolic
Nov 12 at 13:51
add a comment |
1
Are you sure you are running the clock signal? Please add you testbench code to your question so we can help you better
– Unn
Nov 11 at 23:11
crossposted electronics.stackexchange.com/questions/406245/…
– toolic
Nov 12 at 13:51
1
1
Are you sure you are running the clock signal? Please add you testbench code to your question so we can help you better
– Unn
Nov 11 at 23:11
Are you sure you are running the clock signal? Please add you testbench code to your question so we can help you better
– Unn
Nov 11 at 23:11
crossposted electronics.stackexchange.com/questions/406245/…
– toolic
Nov 12 at 13:51
crossposted electronics.stackexchange.com/questions/406245/…
– toolic
Nov 12 at 13:51
add a comment |
2 Answers
2
active
oldest
votes
All signals in verilog simulation are initialized to 'x'. So are the values of A and D. Your second xor is applied to xoy ^ A. Since A is x, the result of this xor is always x. you need to break this loop, as oldfart suggested.
The usual way for doing it is to introduce a reset in the flop, synchronous or asynchronous. Here is an example of a synchronous reset flop:
always @(posedge clk)
if (reset)
q <= 0;
else
q <= D;
So, now, if you set your reset to '1' for at least one posedge of clk and then set it to '0', you will break the loop by pushing a non-'x' value in the data path.
answered Nov 12 at 0:41
Serge
3,4892914
add a comment |
You do not clear your D-FF. The output is X at the start and as you use that in a feedback loop it stays X.
This: wire state=1'b0; does not clear you FF. You have to clear 'q'.
answered Nov 11 at 23:21
Oldfart
2,4142711
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
All signals in verilog simulation are initialized to 'x'. So are the values of A and D. Your second xor is applied to xoy ^ A. Since A is x, the result of this xor is always x. you need to break this loop, as oldfart suggested.
The usual way for doing it is to introduce a reset in the flop, synchronous or asynchronous. Here is an example of a synchronous reset flop:
always @(posedge clk)
if (reset)
q <= 0;
else
q <= D;
So, now, if you set your reset to '1' for at least one posedge of clk and then set it to '0', you will break the loop by pushing a non-'x' value in the data path.
answered Nov 12 at 0:41
Serge
3,4892914
add a comment |
All signals in verilog simulation are initialized to 'x'. So are the values of A and D. Your second xor is applied to xoy ^ A. Since A is x, the result of this xor is always x. you need to break this loop, as oldfart suggested.
The usual way for doing it is to introduce a reset in the flop, synchronous or asynchronous. Here is an example of a synchronous reset flop:
always @(posedge clk)
if (reset)
q <= 0;
else
q <= D;
So, now, if you set your reset to '1' for at least one posedge of clk and then set it to '0', you will break the loop by pushing a non-'x' value in the data path.
answered Nov 12 at 0:41
Serge
3,4892914
add a comment |
All signals in verilog simulation are initialized to 'x'. So are the values of A and D. Your second xor is applied to xoy ^ A. Since A is x, the result of this xor is always x. you need to break this loop, as oldfart suggested.
The usual way for doing it is to introduce a reset in the flop, synchronous or asynchronous. Here is an example of a synchronous reset flop:
always @(posedge clk)
if (reset)
q <= 0;
else
q <= D;
So, now, if you set your reset to '1' for at least one posedge of clk and then set it to '0', you will break the loop by pushing a non-'x' value in the data path.
answered Nov 12 at 0:41
Serge
3,4892914
All signals in verilog simulation are initialized to 'x'. So are the values of A and D. Your second xor is applied to xoy ^ A. Since A is x, the result of this xor is always x. you need to break this loop, as oldfart suggested.
The usual way for doing it is to introduce a reset in the flop, synchronous or asynchronous. Here is an example of a synchronous reset flop:
always @(posedge clk)
if (reset)
q <= 0;
else
q <= D;
So, now, if you set your reset to '1' for at least one posedge of clk and then set it to '0', you will break the loop by pushing a non-'x' value in the data path.
answered Nov 12 at 0:41
Serge
3,4892914
answered Nov 12 at 0:41
Serge
3,4892914
answered Nov 12 at 0:41
Serge
3,4892914
answered Nov 12 at 0:41
Serge
3,4892914
3,4892914
add a comment |
add a comment |
You do not clear your D-FF. The output is X at the start and as you use that in a feedback loop it stays X.
This: wire state=1'b0; does not clear you FF. You have to clear 'q'.
answered Nov 11 at 23:21
Oldfart
2,4142711
add a comment |
You do not clear your D-FF. The output is X at the start and as you use that in a feedback loop it stays X.
This: wire state=1'b0; does not clear you FF. You have to clear 'q'.
answered Nov 11 at 23:21
Oldfart
2,4142711
add a comment |
You do not clear your D-FF. The output is X at the start and as you use that in a feedback loop it stays X.
This: wire state=1'b0; does not clear you FF. You have to clear 'q'.
answered Nov 11 at 23:21
Oldfart
2,4142711
You do not clear your D-FF. The output is X at the start and as you use that in a feedback loop it stays X.
This: wire state=1'b0; does not clear you FF. You have to clear 'q'.
answered Nov 11 at 23:21
Oldfart
2,4142711
answered Nov 11 at 23:21
Oldfart
2,4142711
answered Nov 11 at 23:21
Oldfart
2,4142711
answered Nov 11 at 23:21
Oldfart
2,4142711
2,4142711
add a comment |
add a comment |
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1
Are you sure you are running the clock signal? Please add you testbench code to your question so we can help you better
– Unn
Nov 11 at 23:11
crossposted electronics.stackexchange.com/questions/406245/…
– toolic
Nov 12 at 13:51